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| CD4048BMS December 1992 CMOS Multifunction Expandable 8 Input Gate Pinout CD4048BMS TOP VIEW Features * High-Voltage Type (20V Rating) * Three State Output * Many Logic Functions Available in One Package J (OUTPUT) 1 16 VDD 15 EXPAND 14 A 13 B INPUTS 12 C 11 D 10 Ka 9 Kc * Standardize, Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" INPUTS Kd 2 H3 G4 F5 E6 Kb 7 VSS 8 Functional Diagram BINARY CONTROL INPUTS FUNCTION CONTROL Ka 10 INPUTS A B C D 14 13 12 11 15 6 5 4 3 I J OUTPUT Kb Kc Kd 7 9 2 3 STATE CONTROL Applications * Selection of Up to 8 Logic Functions * Digital Control of Logic * General Purpose Gating Logic - Decoding - Encoding Description CD4048BMS is an 8-input gate having four control inputs. Three binary control inputs - Ka, Kb, and Kc - provide the implementation of eight different logic functions. These functions are OR, NOR, AND, NAND, OR/AND, OR/NAND, AND/OR and AND/ NOR. A fourth control input, Kd, provides the user with a 3-state output. When control input Kd is high, the output is either a logic 1 or a logic 0 depending on the inner states. When control input Kd is low, the output is an open circuit. This feature enables the user to connect this device to a common bus line. In addition to the eight input lines, an EXPAND input is provided that permits the user to increase the number of inputs into a CD4048BMS (see Figure 2). For example, two CD4048BMS's can be cascaded to provided a 16-input multifunction gate. When the EXPAND input is not used, it should be connected to VSS. The CD4048BMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4S H1E H6W EXPAND E F G H INPUTS VSS = 8 VDD = 16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 File Number 3314 7-912 Specifications CD4048BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 0.4 12 0.4 V V V V A A A A A A -55oC o PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7 MAX 0.5 50 0.5 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +25oC, +125oC, -55oC 14.95 VOH > VOL < VDD/2 VDD/2 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-913 Specifications CD4048BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 600 810 200 270 UNITS ns ns ns ns PARAMETER Propagation Delay Ka to Output Transition Time SYMBOL TPHL TPLH TTHL TTLH CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55 C, +25 C +125 C VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125 C -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Ka to Output VIL VIH TPHL1 TPLH1 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC 7 300 240 V ns ns o o o o MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 - MAX 0.25 7.5 0.5 15 0.5 30 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V 7-914 Specifications CD4048BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Inputs to Output SYMBOL TPHL2 TPLH2 CONDITIONS VDD = 5V VDD = 10V VDD = 15V Propagation Delay Kb to Output TPHL3 TPLH3 VDD = 5V VDD = 10V VDD = 15V Propagation Delay Kc to Output TPHL4 TPLH4 VDD = 5V VDD = 10V VDD = 15V Propagation Delay Expand Input to Output TPHL5 TPLH5 VDD = 5V VDD = 10V VDD = 15V Propagation Delay 3 State Kd to Output Transition Time TPHZ, LZ VDD = 5V TPZH, ZL VDD = 10V VDD = 15V TTLH TTHL CIN CO VDD = 10V VDD = 15V Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2 1, 2 TEMPERATURE +25oC +25 C +25oC +25 oC o MIN - MAX 600 300 240 450 170 110 280 100 80 380 180 130 160 70 50 100 80 7 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF +25oC +25oC +25 oC +25o C +25oC +25 oC +25oC +25 C +25o C +25oC +25oC +25 oC o +25oC +25 C +25 oC o Input Capacitance 3 State Output Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record 7-915 Specifications CD4048BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - SSI Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.1A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A, RONDEL10 READ AND RECORD IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 1 1 1 GROUND 2 - 15 8 8, 15 8 VDD 16 2 - 7, 9 - 16 2, 16 2 - 7, 9 - 16 1 9 - 14 3-7 9V -0.5V 50kHz 25kHz 7-916 CD4048BMS Logic Diagrams NOR A B C D E F G H EXP OR/AND A B C D E F G H A B C D E F G H OR A B C D E F G H EXP OR/NAND A B C D E F G H NAND A B C D E F G H EXP AND/OR A B C D E F G H AND A B C D E F G H EXP AND/NOR EXP EXP EXP EXP FIGURE 1. BASIC LOGIC CONFIGURATIONS Ka Ka * Kb 7 * Kc 9 * Kd 2 * * A 14 Kb 10 * B 13 * C 12 * D 11 Kc * EXP 15 Ka Ka Kb Kb Kc Kc VDD Kd Kd Kd * E 6 Kb 1 J * F 5 Kd * G 4 VDD VSS * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK * H 3 VSS FIGURE 2. LOGIC DIAGRAM 7-917 CD4048BMS Logic Diagrams (Continued) NOR 11 12 13 14 15 3 4 5 6 NAND Ka - Kb - Kc 0-0-0 OR 1-0-1 AND/OR AND 1-0-0 AND/NOR 0-0-1 OR/NAND 1-1-1 OR/AND 1-1-0 0-1-1 0-1-0 FIGURE 3. ACTUAL CIRCUIT LOGIC CONFIGURATIONS Applications of Expand Input VDD J (OUTPUT) 1 Kd VDD 2 H3 G4 F5 VDD E6 Kb 7 VSS 8 16 15 14 A 13 B 12 C 11 D 10 9 Ka Kc VSS 12 - INPUT OR/AND GATE J = (A+B+C+D) . (E+F+G+H) . (X1+X2+X3+X4) VSS X1 X2 X3 X4 OR FUNCTION VDD OUTPUT VDD Kd 1 2 16 15 14 A1 13 B1 12 C1 11 D1 10 Ka 9 Kc VSS VDD Kd J(OUTPUT) 1 2 VDD 16 15 EXP 1/2 CD4002A H1 3 G1 4 F1 5 E1 6 Kb 7 8 H2 3 G2 4 F2 5 E2 6 Kb 7 8 VSS 14 A2 13 B2 12 C2 11 D2 10 Ka 9 Kc VSS VSS VDD 16 - INPUT NOR GATE J = A1 +B1 +C1 +D1 +E1 +F1 +G1 +H1 +A2 +B2 +C2 +D2 +E2 +F2 +G2 +H2 FIGURE 4. 12 INPUT OR/AND GATE FIGURE 5. 16 INPUT NOR GATE IMPLEMETATION OF EXPAND INPUT FOR 9 OR MORE INPUTS OUTPUT FUNCTION NOR OR AND NAND OR/AND OR/NAND AND/NOR AND/OR FUNCTION NEEDED AT EXPAND INPUT OR OR NAND NAND NOR NOR AND AND OUTPUT BOOLEAN EXPRESSION J=(A+B+C+D+E+F+G+H)+(EXP) J=(A+B+C+D+E+F+G+H)+(EXP) J=(ABCDEFGH)*(EXP) J=(ABCDEFGH)*(EXP) J=(A+B+C+D)*(E+F+G+H)*(EXP) J=(A+B+C+D)*(E+F+G+H)*(EXP) J=(ABCD)+(EFGH)+(EXP) J=(ABCD)+(EFGH)+(EXP) NOTES: 1. (EXP) designates the EXPAND function (i.e., X1 + X2 + . . .XN). 2. Refer to FUNCTION TRUTH TABLE for connection of unused inputs. 7-918 CD4048BMS FUNCTION TRUTH TABLE OUTPUT FUNCTION NOR OR OR/AND OR/NAND AND NAND AND/NOR AND/OR BOOLEAN EXPRESSION J=A+B+C+D+E+F+G+H J=A+B+C+D+E+F+G+H J=(A+B+C+D)*(E+F+G+H) J=(A+B+C+D)*(E+F+G+H) J=ABCDEFGH J=ABCDEFGH J=ABCD+EFGH J=ABCD+EFGH Ka 0 0 0 0 1 1 1 1 Kb 0 0 1 1 0 0 1 1 Kc 0 1 0 1 0 1 0 1 UNUSED INPUT* VSS VSS VSS VSS VDD VDD VDD VDD Kd = 1 Normal Inverter Action Kd = 0 High Impedance Output EXPAND Input = 0 *See Figures 1, 2, 3, 4 and 5 Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 6. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 7. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-919 CD4048BMS Typical Performance Characteristics DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 0 -5 -10 -15 -10V -20 -25 -15V -30 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) (Continued) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -10V -10 -15V -15 FIGURE 8. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC FIGURE 9. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (fTHL, fTLH) (ns) 300 SUPPLY VOLTAGE (VDD) = 5V 200 SUPPLY VOLTAGE (VDD) = 5V 200 10V 150 100 10V 50 15V 100 15V 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 10. TYPICAL PROPAGATION DELAY TIME (LOGIC INPUTS TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE 105 8 DYNAMIC POWER DISSIPATION (PD) (W) 6 4 2 FIGURE 11. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF SUPPLY VOLTAGE (VDD) = 5V 10 8 6 4 2 4 10V 15V 103 8 6 4 2 102 8 6 4 2 10 2 4 68 1 103 10 102 INPUT FREQUENCY (fI) (kHz) 2 4 68 2 4 68 2 4 68 104 2 4 68 105 FIGURE 12. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 7-920 CD4048BMS Test Circuits and Wave Forms PULSE GENERATOR VDD 500F OUTPUT 1 2 3 4 5 6 CL 7 8 16 15 14 13 5 12 6 11 7 10 8 9 9 10 11 12 0.1F CL = 15pF OR 50pF 2 3 4 15 14 13 INPUT 1 16 H VDD VDD FIGURE 13. DYNAMIC POWER DISSIPATION TEST CIRCUIT FIGURE 14. TEST CIRCUIT FOR tPHL, tTHL, AND tTHL (AND) MEASUREMENTS 50pF VDD (tPLZ) (tPZL) VSS (tPHZ) (tPZH) 16 15 14 Kd 50% 1 PULSE GENERATOR Kd 2 3 4 5 6 7 8 (AND) 13 12 11 10 9 VDD VSS tPZL OUTPUT tPZH 90% tPLZ 10% 90% OUTPUT 10% tPHL FIGURE 15. TEST CIRCUIT FOR tPZL, tPZH, tPLZ, AND tPHZ (AND) FIGURE 16. WAVEFORMS FOR tPZL, tPZH, tPLZ AND tPHZ (AND) 50% INPUT INPUT 50% 50% OUTPUT tPHL OUTPUT tTHL 90% 10% tTLH FIGURE 17. WAVEFORMS FOR tPHL AND tPHL (AND) FIGURE 18. WAVEFORMS FOR tTHL AND tTLH (AND) 7-921 CD4048BMS Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kA - 14kA, AL. 10.4kA - 15.6kA, Silane 0.0198 inches - 0.0218 inches BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 922 |
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